The risk of fracture in Interlayer Dielectric (ILD) stack is evaluated for various configurations of flip-chip packages in this paper. A novel analysis on the mechanical behavior of package with a focus on die surface provides the insights into the critical deformation state as well as its location. In Controlled Collapse Chip Connection (C4) process, the reflow phase involves a cooling of the entire package from the reflow temperature to room temperature, and is critical for package induced die cracking (Chip-Package Interaction or CPI). We use commercial finite element software ABAQUS to construct local sub-models of ILD region from global models of a representative 3-D package with component materials modeled as being temperature dependent elastic or elasto-plastic as appropriate. The risk of ILD fracture is systematically investigated using the described approach.
- Electronic and Photonic Packaging Division
Nature of Package-Induced Deformation and the Risk of Fracture in Low-k Dielectric Stacks
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Lin, H, Tambat, A, Claydon, I, Subbarayan, G, Jung, DY, & Sammakia, B. "Nature of Package-Induced Deformation and the Risk of Fracture in Low-k Dielectric Stacks." Proceedings of the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1. Portland, Oregon, USA. July 6–8, 2011. pp. 351-356. ASME. https://doi.org/10.1115/IPACK2011-52258
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