Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology and its applications to accurately and efficiently predict power and temperature distribution for 3D ICs.
- Electronic and Photonic Packaging Division
IC-Package Thermal Co-Analysis in 3D IC Environment
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Pan, SH, Chang, N, & Zheng, J. "IC-Package Thermal Co-Analysis in 3D IC Environment." Proceedings of the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 2. Portland, Oregon, USA. July 6–8, 2011. pp. 335-341. ASME. https://doi.org/10.1115/IPACK2011-52240
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