Understanding the effect of high current density on void formation and growth and relating the size of the void to the resulting electrical/mechanical failure is a critical need at the present time to ensure reliable functioning of flip-chip packages. In general, toward this end, the modeling and simulation of geometrical evolution of current induced voids have been relatively few. Simulations considering the coupled effects of mass transport through mechanisms of surface and bulk diffusion under the influence of electrical, thermal, and stress fields in solder joints leading to eventual electromigration failure do not appear to be common. In this study, we develop a phase field model for the evolution of voids under electrical, thermal, and stress fields in a flip-chip solder interconnect. We derive the equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress, and electric potential, considering both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using a finite element code written in the PYTHON language, coupled with a commercial finite element solver from which we obtain the electrical, thermal, and stress fields driving the void motion. We demonstrate the implemented methodology through simulations of void evolution in flip-chip solder joints under the effects of mechanical/electrical fields and surface/bulk diffusion.
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Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects
Daniel Pantuso
Daniel Pantuso
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Subramanya Sadasiva
Ganesh Subbarayan
Lei Jiang
Daniel Pantuso
J. Electron. Packag. Jun 2012, 134(2): 020907 (9 pages)
Published Online: June 11, 2012
Article history
Received:
September 20, 2011
Revised:
February 13, 2012
Online:
June 11, 2012
Published:
June 11, 2012
Citation
Sadasiva, S., Subbarayan, G., Jiang, L., and Pantuso, D. (June 11, 2012). "Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects." ASME. J. Electron. Packag. June 2012; 134(2): 020907. https://doi.org/10.1115/1.4006707
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